「315-5313」の編集履歴（バックアップ）一覧はこちら
315-5313 - (2011/10/25 (火) 16:38:46) の１つ前との変更点
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== 概要 ==
315-5313は[[SYSTEM C,C2>SYSTEM C]]などに使われているLSI。メガドライブのVDP。
== 仕様 ==
&bold(){[[SYSTEM C2>SYSTEM C]]に実装されている315-5313}
#image(http://www40.atwiki.jp/arcadegames/?cmd=upload&act=open&page=315-5313&file=315-5313_01.jpg,width=320,height=273,title=SYSTEM C2に実装されている315-5313,http://www40.atwiki.jp/arcadegames/?cmd=upload&act=open&page=315-5313&file=315-5313_01.jpg,blank)
・315-5313 (YAMAHA)
・128ピンQFP
== ピンアサインなど解析資料 ==
・[[VDP pin assignments 315-5313 information (C) 2008 Charles MacDonald>>http://cgfm2.emuviews.com/txt/vdppin.txt]]
・[[VDP pin assignments 315-5313 information (C) 2008 Charles MacDonald (BACKUP)>>http://www40.atwiki.jp/arcadegames/?cmd=upload&act=open&page=315-5313&file=vdppin.txt]]
|ピン番号|ピン名称|機能|
|001|VRAM SD0|Serial data bus.|
|002|VRAM SD1|Serial data bus.|
|003|VRAM SD2|Serial data bus.|
|004|VRAM SD3|Serial data bus.|
|005|VRAM SD4|Serial data bus.|
|006|VRAM SD5|Serial data bus.|
|007|VRAM SD6|Serial data bus.|
|008|VRAM SD7|Serial data bus.|
|009|(N.C.)||
|010|VRAM /SE_0|Serial data bus /OE|
|011|VRAM SC|Serial clock.|
|012|VRAM /RAS_1|Row address strobe.|
|013|VRAM /CAS_1|Column address strobe.|
|014|(N.C.)||
|015|VRAM /WE_0 <- /WE_1?|Common write strobe.|
|016|VRAM /OE_1|Common read strobe.|
|017|GND||
|018|(N.C.)||
|019|(N.C.)||
|020|(N.C.)||
|021|(N.C.)||
|022|(N.C.)||
|023|(N.C.)||
|024|(N.C.)||
|025|(N.C.)||
|026|AGC||
|027|R-VIDEO||
|028|G-VIDEO||
|029|B-VIDEO||
|030|AVC||
|031|VRAM AD0|Parallel address/data bus.|
|032|VRAM AD1|Parallel address/data bus.|
|033|VRAM AD2|Parallel address/data bus.|
|034|VRAM AD3|Parallel address/data bus.|
|035|VRAM AD4|Parallel address/data bus.|
|036|VRAM AD5|Parallel address/data bus.|
|037|VRAM AD6|Parallel address/data bus.|
|038|VRAM AD7|Parallel address/data bus.|
|039|/YS <- /Y1? |0=Transparent pixel, 1=Opaque pixel|
|040|SPA/B|0= Sprite pixel.&br()1= Non-sprite pixel.|
|||/Y1 and SPA/B can be decoded as follows&br()&nowiki(){|}/Y1&nowiki(){|}A/B&nowiki(){|}&br()&nowiki(){|}0&nowiki(){|}0&nowiki(){|}:Transparent pixel from any layer.&br()&nowiki(){|}0&nowiki(){|}1&nowiki(){|}:(This condition never occurs)&br()&nowiki(){|}1&nowiki(){|}0&nowiki(){|}:Opaque pixel from sprite layer.&br()&nowiki(){|}1&nowiki(){|}1&nowiki(){|}:Opaque pixel from background or backdrop layers.|
|041|/VSYNC||
|042|/C-SYNC||
|043|/HSYNC||
|044|/HL|Horizontal counter latch enable.&br()On a negative transition the horizontal counter is latched and can be read back by the CPU. It remains latched as long as /HL is held low, otherwise it is free-running.|
|045|SEL0|0=VDP operates in Mark-III compatibility mode.&br()1=VDP operates in normal mode.|
|046|/PAL|0=VDP generates PAL compatible display timings.&br()1=VDP generates NTSC compatible display timings.|
|047|/RESET|Reset input.|
|048|SEL1|Unknown.&br()Tied to GND in Sega Genesis, Mega Play.&br()Tied to +5V in System C2 and System 18.|
|049|/CLK1|Outputs MCLK/7&br()When MCLK=53.694175 MHz. => /CLK1=7.67 MHz (68K and YM2612 clock)|
|050|SBCR|Outputs MCLK /15 (when /PAL=H)&br()Outputs MCLK/12 (when /PAL=L)&br()MCLK=53.694175 MHz. => SBCR=3.58 MHz (/PAL=H, NTSC color subcarrier)&br()SBCR=4.48 MHz (/PAL=L, PAL color subcarrier)|
|051|CLK0|Outputs MCLK/15&br()When MCLK=53.694175 MHz. =>CLK0=3.58 MHz (Z80 clock).|
|052|MCLK|Master clock input.&br()In a typical system MCLK is 53.694175 MHz.|
|053|EDCLK|Unknown.&br()When MCLK=53.694175 MHz. =>Unknown.|
|054|+5V||
|055|68000 D0|Data bus.|
|056|68000 D1|Data bus.|
|057|68000 D2|Data bus.|
|058|68000 D3|Data bus.|
|059|68000 D4|Data bus.|
|060|68000 D5|Data bus.|
|061|68000 D6|Data bus.|
|062|68000 D7|Data bus.|
|063|68000 D8|Data bus.|
|064|68000 D9|Data bus.|
|065|68000 D10|Data bus.|
|066|68000 D11|Data bus.|
|067|68000 D12|Data bus.|
|068|68000 D13|Data bus.|
|069|68000 D14|Data bus.|
|070|68000 D15|Data bus.|
|071|68000 A1|Address bus.|
|072|68000 A2|Address bus.|
|073|68000 A3|Address bus.|
|074|68000 A4|Address bus.|
|075|68000 A5|Address bus.|
|076|68000 A6|Address bus.|
|077|68000 A7|Address bus.|
|078|68000 A8|Address bus.|
|079|68000 A9|Address bus.|
|080|68000 A10|Address bus.|
|081|68000 A11|Address bus.|
|082|68000 A12|Address bus.|
|083|68000 A13|Address bus.|
|084|68000 A14|Address bus.|
|085|68000 A15|Address bus.|
|086|68000 A16|Address bus.|
|087|68000 A17|Address bus.|
|088|68000 A18|Address bus.|
|089|68000 A19|Address bus.|
|090|68000 A20|Address bus.|
|091|68000 A21|Address bus.|
|092|68000 A22|Address bus.|
|093|68000 A23|Address bus.|
|094|AVS||
|095|PSG|Sound output.&br()PSG is the analog audio output from the SN76489-alike programmable sound generator in the VDP. AVS and AGS should be tied to +5V and GND respectively.|
|096|AGS||
|097|GND||
|098|Z80 /INT|Interrupt request.|
|099|68000 /BR|Bus request.|
|100|68000 /BGACK|Bus grant acknowledge.|
|101|68000 /BG|Bus grant.|
|102|/MRE0|Unknown.&br()Tied to +5V in System C2.&br()Controlled by the glue logic chip in the Genesis/MegaDrive.|
|103|/INTAK|Asserted to acknowledge a VDP-generated interrupt on IPL2-1.&br()An external circuit would assert this when FC2-0 are high and /AS is low.|
|104|68000 /IPL1|Interrupt priority level, bit 1|
|105|68000 /IPL2|Interrupt priority level, bit 2|
|106|Z80 /IREQ|I/O access.|
|107|Z80 /ZRD|Read strobe.|
|108|Z80 /ZWR|Write strobe.|
|109|Z80 /M1|Opcode fetch strobe.|
|110|68000 /AS|Address strobe.|
|111|68000 /UDS|Upper data strobe.|
|112|68000 /LDS|Lower data strobe.|
|113|68000 R//W|Read/write indicator.|
|114|68000 /DTAK|Data acknowledge.|
|115|/UWR|Asserted when /UDS=L, /R/W=L.&br()Used as the upper byte lane strobe.|
|116|/LWR|Asserted when /LDS=L, /R/W=L.&br()Used as the lower byte lane strobe.|
|117|/OE0|Asserted when /R/W=H within address range E00000-FFFFFF.&br()During DMA, it is asserted for 000000-FFFFFF. Hardware depending on it's restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range.&br()Typically used as work RAM /OE with RAM mapped to E00000-FFFFFF.&br()Refresh behavior&br()Periodically /RAS0 is delayed, and an extra /OE0 pulse is added.|
|118|/CAS0|Asserted when /AS=L, /R/W=H within address range 000000-DFFFFF.&br()During DMA, it is asserted for 000000-FFFFFF. Hardware depending on it's restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range.&br()Because this signal overlaps the VDP area at $C00000-$DFFFFF,it is insufficient to use directly as a chip select despite being qualified by /AS.&br()If it was (for example) gated with A23, it could be used directly as ROM /OE for fast ROM access when ROM /CS is tied low.&br()Typically used as a read strobe, and the address decoding logic restricts other devices from responding to it when an address is within the VDP range.|
|119|/RAS0|Asserted when /AS=L within address range E00000-FFFFFF.&br()During DMA, it is asserted for 800000-FFFFFF. Hardware depending on it's restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range.&br()Typically used as work RAM /CS with RAM mapped to E00000-FFFFFF.&br()Periodically the VDP will stretch a /RAS0 cycle longer than normal, and insert an extra /OE0 pulse. This may be to provide a refresh cycle for pseudo-static RAMs.|
|120|VD0|Pixel, bit 0|
|121|VD1|Pixel, bit 1|
|122|VD2|Pixel, bit 2|
|123|VD3|Pixel, bit 3|
|124|VD4|Palette, bit 0|
|125|VD5|Palette, bit 1|
|126|VD6|Shadow effect (0= not applied, 1= applied)|
|127|VD7|Hilight effect (0= not applied, 1= applied)|
|||VD7 and VD6 can be decoded as follows&br()&nowiki(){|}VD7&nowiki(){|}VD6&nowiki(){|}&br()&nowiki(){|}0&nowiki(){|}0&nowiki(){|}:Normal&br()&nowiki(){|}0&nowiki(){|}1&nowiki(){|}:Shadow&br()&nowiki(){|}1&nowiki(){|}0&nowiki(){|}:Hilight&br()&nowiki(){|}1&nowiki(){|}1&nowiki(){|}:(This condition never occurs)|
|128|+5V||
|-|Z80 interface|It is not clear how the VDP knows when to respond to the Z80 for accesses to $7F00-$7F1F, which map to $C00000-$C0001F. It could be that the glue logic chip forwards this request on the 68000 bus.&br() When in Mark-III compatibility mode, the Z80 address and data bus are routed to the 68000 address and data bus. This way the VDP can check /IREQ to determine when ports $40-$7F and $80-BF are being accessed, and respond to them accordingly.|
|-|Video sync signals|The function of /VSYNC is defined by bit 6 of VDC register $0C:&br()&br()0= Pin outputs vertical sync. pulse.&br()1= Pin outputs pixel clock.&br()The function of /HSYNC is defined by bit 5 of VDC register $8C:&br()0= Pin outputs horizontal sync. pulse.&br()1= Pin is fixed to 'H'&br()/C-SYNC outputs a composite sync signal. It is TTL like /VSYNC and /HSYNC.|
|-|Video output|R-VIDEO,G-VIDEO,B-VIDEO are the analog RGB outputs. AGC and AVC should be tied to +5V and GND respectively.|
|-|Color bus|The color bus outputs information about the pixel data being displayed:&br()/Y1 : 0= Transparent pixel, 1= Opaque pixel.&br()SPA/B : 0= Sprite pixel, 1= Non-sprite pixel.&br()VD7 : Hilight effect (0= not applied, 1= applied).&br()VD6 : Shadow effect (0= not applied, 1= applied).&br()VD5 : Palette, bit 1&br()VD4 : Palette, bit 0&br()VD3 : Pixel, bit 3&br()VD2 : Pixel, bit 2&br()VD1 : Pixel, bit 1&br()VD0 : Pixel, bit 0|
|-|Unknown pins|Pins 9, 14, 18-25 seem to be no-connects and have no known function.|
・[[Genesis 3 circuit schematic>>http://www.sega-16.com/forum/showthread.php?6370-Project-Rebirth-Take-2]]
== リンク ==
・[[セガ]](SEGA)
・[[SYSTEM C]]
----
== 概要 ==
315-5313は[[SYSTEM C,C2>SYSTEM C]]などに使われているLSI。メガドライブのVDP。
== 仕様 ==
|&bold(){[[SYSTEM C2>SYSTEM C]]に実装されている315-5313}|&bold(){MEGA DRIVE(IC BD M5)に実装されている315-5313A}|
|&image(http://www40.atwiki.jp/arcadegames/?cmd=upload&act=open&page=315-5313&file=315-5313_01.jpg,width=320,height=273,title=SYSTEM C2に実装されている315-5313,http://www40.atwiki.jp/arcadegames/?cmd=upload&act=open&page=315-5313&file=315-5313_01.jpg,blank)|&image(http://www40.atwiki.jp/arcadegames/?cmd=upload&act=open&page=315-5313&file=315-5313A_01.jpg,width=320,height=273,title=SYSTEM C2に実装されている315-5313,http://www40.atwiki.jp/arcadegames/?cmd=upload&act=open&page=315-5313&file=315-5313A_01.jpg,blank)|
・315-5313 (YAMAHA)
・128ピンQFP
== ピンアサインなど解析資料 ==
・[[VDP pin assignments 315-5313 information (C) 2008 Charles MacDonald>>http://cgfm2.emuviews.com/txt/vdppin.txt]]
・[[VDP pin assignments 315-5313 information (C) 2008 Charles MacDonald (BACKUP)>>http://www40.atwiki.jp/arcadegames/?cmd=upload&act=open&page=315-5313&file=vdppin.txt]]
|ピン番号|ピン名称|機能|
|001|VRAM SD0|Serial data bus.|
|002|VRAM SD1|Serial data bus.|
|003|VRAM SD2|Serial data bus.|
|004|VRAM SD3|Serial data bus.|
|005|VRAM SD4|Serial data bus.|
|006|VRAM SD5|Serial data bus.|
|007|VRAM SD6|Serial data bus.|
|008|VRAM SD7|Serial data bus.|
|009|(N.C.)||
|010|VRAM /SE_0|Serial data bus /OE|
|011|VRAM SC|Serial clock.|
|012|VRAM /RAS_1|Row address strobe.|
|013|VRAM /CAS_1|Column address strobe.|
|014|(N.C.)||
|015|VRAM /WE_0 <- /WE_1?|Common write strobe.|
|016|VRAM /OE_1|Common read strobe.|
|017|GND||
|018|(N.C.)||
|019|(N.C.)||
|020|(N.C.)||
|021|(N.C.)||
|022|(N.C.)||
|023|(N.C.)||
|024|(N.C.)||
|025|(N.C.)||
|026|AGC||
|027|R-VIDEO||
|028|G-VIDEO||
|029|B-VIDEO||
|030|AVC||
|031|VRAM AD0|Parallel address/data bus.|
|032|VRAM AD1|Parallel address/data bus.|
|033|VRAM AD2|Parallel address/data bus.|
|034|VRAM AD3|Parallel address/data bus.|
|035|VRAM AD4|Parallel address/data bus.|
|036|VRAM AD5|Parallel address/data bus.|
|037|VRAM AD6|Parallel address/data bus.|
|038|VRAM AD7|Parallel address/data bus.|
|039|/YS <- /Y1? |0=Transparent pixel, 1=Opaque pixel|
|040|SPA/B|0= Sprite pixel.&br()1= Non-sprite pixel.|
|||/Y1 and SPA/B can be decoded as follows&br()&nowiki(){|}/Y1&nowiki(){|}A/B&nowiki(){|}&br()&nowiki(){|}0&nowiki(){|}0&nowiki(){|}:Transparent pixel from any layer.&br()&nowiki(){|}0&nowiki(){|}1&nowiki(){|}:(This condition never occurs)&br()&nowiki(){|}1&nowiki(){|}0&nowiki(){|}:Opaque pixel from sprite layer.&br()&nowiki(){|}1&nowiki(){|}1&nowiki(){|}:Opaque pixel from background or backdrop layers.|
|041|/VSYNC||
|042|/C-SYNC||
|043|/HSYNC||
|044|/HL|Horizontal counter latch enable.&br()On a negative transition the horizontal counter is latched and can be read back by the CPU. It remains latched as long as /HL is held low, otherwise it is free-running.|
|045|SEL0|0=VDP operates in Mark-III compatibility mode.&br()1=VDP operates in normal mode.|
|046|/PAL|0=VDP generates PAL compatible display timings.&br()1=VDP generates NTSC compatible display timings.|
|047|/RESET|Reset input.|
|048|SEL1|Unknown.&br()Tied to GND in Sega Genesis, Mega Play.&br()Tied to +5V in System C2 and System 18.|
|049|/CLK1|Outputs MCLK/7&br()When MCLK=53.694175 MHz. => /CLK1=7.67 MHz (68K and YM2612 clock)|
|050|SBCR|Outputs MCLK /15 (when /PAL=H)&br()Outputs MCLK/12 (when /PAL=L)&br()MCLK=53.694175 MHz. => SBCR=3.58 MHz (/PAL=H, NTSC color subcarrier)&br()SBCR=4.48 MHz (/PAL=L, PAL color subcarrier)|
|051|CLK0|Outputs MCLK/15&br()When MCLK=53.694175 MHz. =>CLK0=3.58 MHz (Z80 clock).|
|052|MCLK|Master clock input.&br()In a typical system MCLK is 53.694175 MHz.|
|053|EDCLK|Unknown.&br()When MCLK=53.694175 MHz. =>Unknown.|
|054|+5V||
|055|68000 D0|Data bus.|
|056|68000 D1|Data bus.|
|057|68000 D2|Data bus.|
|058|68000 D3|Data bus.|
|059|68000 D4|Data bus.|
|060|68000 D5|Data bus.|
|061|68000 D6|Data bus.|
|062|68000 D7|Data bus.|
|063|68000 D8|Data bus.|
|064|68000 D9|Data bus.|
|065|68000 D10|Data bus.|
|066|68000 D11|Data bus.|
|067|68000 D12|Data bus.|
|068|68000 D13|Data bus.|
|069|68000 D14|Data bus.|
|070|68000 D15|Data bus.|
|071|68000 A1|Address bus.|
|072|68000 A2|Address bus.|
|073|68000 A3|Address bus.|
|074|68000 A4|Address bus.|
|075|68000 A5|Address bus.|
|076|68000 A6|Address bus.|
|077|68000 A7|Address bus.|
|078|68000 A8|Address bus.|
|079|68000 A9|Address bus.|
|080|68000 A10|Address bus.|
|081|68000 A11|Address bus.|
|082|68000 A12|Address bus.|
|083|68000 A13|Address bus.|
|084|68000 A14|Address bus.|
|085|68000 A15|Address bus.|
|086|68000 A16|Address bus.|
|087|68000 A17|Address bus.|
|088|68000 A18|Address bus.|
|089|68000 A19|Address bus.|
|090|68000 A20|Address bus.|
|091|68000 A21|Address bus.|
|092|68000 A22|Address bus.|
|093|68000 A23|Address bus.|
|094|AVS||
|095|PSG|Sound output.&br()PSG is the analog audio output from the SN76489-alike programmable sound generator in the VDP. AVS and AGS should be tied to +5V and GND respectively.|
|096|AGS||
|097|GND||
|098|Z80 /INT|Interrupt request.|
|099|68000 /BR|Bus request.|
|100|68000 /BGACK|Bus grant acknowledge.|
|101|68000 /BG|Bus grant.|
|102|/MRE0|Unknown.&br()Tied to +5V in System C2.&br()Controlled by the glue logic chip in the Genesis/MegaDrive.|
|103|/INTAK|Asserted to acknowledge a VDP-generated interrupt on IPL2-1.&br()An external circuit would assert this when FC2-0 are high and /AS is low.|
|104|68000 /IPL1|Interrupt priority level, bit 1|
|105|68000 /IPL2|Interrupt priority level, bit 2|
|106|Z80 /IREQ|I/O access.|
|107|Z80 /ZRD|Read strobe.|
|108|Z80 /ZWR|Write strobe.|
|109|Z80 /M1|Opcode fetch strobe.|
|110|68000 /AS|Address strobe.|
|111|68000 /UDS|Upper data strobe.|
|112|68000 /LDS|Lower data strobe.|
|113|68000 R//W|Read/write indicator.|
|114|68000 /DTAK|Data acknowledge.|
|115|/UWR|Asserted when /UDS=L, /R/W=L.&br()Used as the upper byte lane strobe.|
|116|/LWR|Asserted when /LDS=L, /R/W=L.&br()Used as the lower byte lane strobe.|
|117|/OE0|Asserted when /R/W=H within address range E00000-FFFFFF.&br()During DMA, it is asserted for 000000-FFFFFF. Hardware depending on it's restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range.&br()Typically used as work RAM /OE with RAM mapped to E00000-FFFFFF.&br()Refresh behavior&br()Periodically /RAS0 is delayed, and an extra /OE0 pulse is added.|
|118|/CAS0|Asserted when /AS=L, /R/W=H within address range 000000-DFFFFF.&br()During DMA, it is asserted for 000000-FFFFFF. Hardware depending on it's restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range.&br()Because this signal overlaps the VDP area at $C00000-$DFFFFF,it is insufficient to use directly as a chip select despite being qualified by /AS.&br()If it was (for example) gated with A23, it could be used directly as ROM /OE for fast ROM access when ROM /CS is tied low.&br()Typically used as a read strobe, and the address decoding logic restricts other devices from responding to it when an address is within the VDP range.|
|119|/RAS0|Asserted when /AS=L within address range E00000-FFFFFF.&br()During DMA, it is asserted for 800000-FFFFFF. Hardware depending on it's restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range.&br()Typically used as work RAM /CS with RAM mapped to E00000-FFFFFF.&br()Periodically the VDP will stretch a /RAS0 cycle longer than normal, and insert an extra /OE0 pulse. This may be to provide a refresh cycle for pseudo-static RAMs.|
|120|VD0|Pixel, bit 0|
|121|VD1|Pixel, bit 1|
|122|VD2|Pixel, bit 2|
|123|VD3|Pixel, bit 3|
|124|VD4|Palette, bit 0|
|125|VD5|Palette, bit 1|
|126|VD6|Shadow effect (0= not applied, 1= applied)|
|127|VD7|Hilight effect (0= not applied, 1= applied)|
|||VD7 and VD6 can be decoded as follows&br()&nowiki(){|}VD7&nowiki(){|}VD6&nowiki(){|}&br()&nowiki(){|}0&nowiki(){|}0&nowiki(){|}:Normal&br()&nowiki(){|}0&nowiki(){|}1&nowiki(){|}:Shadow&br()&nowiki(){|}1&nowiki(){|}0&nowiki(){|}:Hilight&br()&nowiki(){|}1&nowiki(){|}1&nowiki(){|}:(This condition never occurs)|
|128|+5V||
|-|Z80 interface|It is not clear how the VDP knows when to respond to the Z80 for accesses to $7F00-$7F1F, which map to $C00000-$C0001F. It could be that the glue logic chip forwards this request on the 68000 bus.&br() When in Mark-III compatibility mode, the Z80 address and data bus are routed to the 68000 address and data bus. This way the VDP can check /IREQ to determine when ports $40-$7F and $80-BF are being accessed, and respond to them accordingly.|
|-|Video sync signals|The function of /VSYNC is defined by bit 6 of VDC register $0C:&br()&br()0= Pin outputs vertical sync. pulse.&br()1= Pin outputs pixel clock.&br()The function of /HSYNC is defined by bit 5 of VDC register $8C:&br()0= Pin outputs horizontal sync. pulse.&br()1= Pin is fixed to 'H'&br()/C-SYNC outputs a composite sync signal. It is TTL like /VSYNC and /HSYNC.|
|-|Video output|R-VIDEO,G-VIDEO,B-VIDEO are the analog RGB outputs. AGC and AVC should be tied to +5V and GND respectively.|
|-|Color bus|The color bus outputs information about the pixel data being displayed:&br()/Y1 : 0= Transparent pixel, 1= Opaque pixel.&br()SPA/B : 0= Sprite pixel, 1= Non-sprite pixel.&br()VD7 : Hilight effect (0= not applied, 1= applied).&br()VD6 : Shadow effect (0= not applied, 1= applied).&br()VD5 : Palette, bit 1&br()VD4 : Palette, bit 0&br()VD3 : Pixel, bit 3&br()VD2 : Pixel, bit 2&br()VD1 : Pixel, bit 1&br()VD0 : Pixel, bit 0|
|-|Unknown pins|Pins 9, 14, 18-25 seem to be no-connects and have no known function.|
・[[Genesis 3 circuit schematic>>http://www.sega-16.com/forum/showthread.php?6370-Project-Rebirth-Take-2]]
== リンク ==
・[[セガ]](SEGA)
・[[SYSTEM C]]
----
