言語/verilog/リファレンス/予約語 - MoriLab.

Verilog HDL 1995 予約語(102)

casex primitive repeat supply0
always casez event macromodule supply1
edge rnmos table
else medium rpmos
end initial rtran task
and endcase inout module rtranif0 vectored
input nand pull0 rtranif1
negedge pull1 scalared time
cmos for pulldown wait
assign endfunction force nmos pullup
integer nor tran wand
forever tranif0 weak0
begin fork not tranif1 weak1
endmodule join notif0 small while
function notif1 tri
endprimitive specify tri0 wire
large or specparam tri1
highz0 output rcmos triand
buf deassign highz1 real trior wor
bufif0 default endspecify if realtime strong0 trireg xnor
bufif1 defparam endtable parameter strong1 xor
endtask ifnone pmos reg
case disable posedge release

verilog 2001 予約語(123)

casex primitive repeat supply0
always casez event macromodule supply1 unsigned
cell edge incdir rnmos table use
else include medium rpmos
end initial rtran task
and endcase inout module rtranif0 vectored
input nand pull0 rtranif1
negedge pull1 scalared time
cmos endconfig for instance pulldown wait
assign config endfunction force nmos pullup
automatic endgenerate integer nor pulsestyle_ondetect tran wand
forever noshowcancelled pulsestyle_onevent showcancelled tranif0 weak0
begin fork not signed tranif1 weak1
endmodule join notif0 small while
function notif1 tri
endprimitive generate specify tri0 wire
genvar large or specparam tri1
highz0 liblist output rcmos triand
buf deassign highz1 library real trior wor
bufif0 default endspecify if realtime strong0 trireg xnor
bufif1 defparam endtable localparam parameter strong1 xor
design endtask ifnone pmos reg
case disable posedge release

SystemVerilog 3.0 予約語(166)

casex enum longreal primitive repeat supply0 unique
always casez do event import macromodule priority return supply1 unsigned
always_comb cell edge incdir process rnmos table use
always_ff else export include medium rpmos
always_latch changed end initial modport rtran task
and char endcase extern inout module rtranif0 vectored
assert input nand pull0 rtranif1
assert_strobe negedge pull1 scalared time void
cmos endconfig for instance pulldown timeprecision wait
assign config endfunction force int nmos pullup shortint timeunit
automatic const endgenerate integer nor pulsestyle_ondetect shortreal tran wand
forever interface noshowcancelled pulsestyle_onevent showcancelled tranif0 weak0
begin endinterface fork not signed tranif1 weak1
continue endmodule forkjoin join notif0 small transition while
function notif1 tri
endprimitive generate specify tri0 wire
bit genvar large or specparam tri1
break highz0 liblist output rcmos static triand
buf deassign highz1 library real trior wor
bufif0 default endspecify if packed realtime strong0 trireg xnor
bufif1 defparam endtable iff localparam parameter strong1 type xor
byte design endtask ifnone logic pmos reg struct typedef
case disable endtransition longint posedge release union

SystemVerilog 3.1 予約語(202)

alias casex dist enum longreal primitive repeat supply0 unique
always casez do event import macromodule priority return supply1 unsigned
always_comb cell edge incdir process rnmos table use
always_ff chandle else export include medium program rpmos
always_latch changed end extends initial modport property rtran task var
and char endcase extern inout module protected rtranif0 this vectored
assert class endclass final input nand pull0 rtranif1 throughout virtual
assert_strobe clocking endclocking first_match inside negedge pull1 scalared time void
cmos endconfig for instance new pulldown sequence timeprecision wait
assign config endfunction force int nmos pullup shortint timeunit wait_order
automatic const endgenerate integer nor pulsestyle_ondetect shortreal tran wand
before constraint forever interface noshowcancelled pulsestyle_onevent showcancelled tranif0 weak0
begin context endinterface fork intersect not pure signed tranif1 weak1
bind continue endmodule forkjoin join notif0 rand small transition while
cover function join_any notif1 randc solve tri
endprimitive generate join_none null specify tri0 wire
bit endprogram genvar large or specparam tri1 with
break endproperty highz0 liblist output rcmos static triand within
buf deassign endsequence highz1 library real string trior wor
bufif0 default endspecify if local packed realtime strong0 trireg xnor
bufif1 defparam endtable iff localparam parameter ref strong1 type xor
byte design endtask ifnone logic pmos reg struct typedef
case disable endtransition longint posedge release super union

SystemVerilog 3.1a 予約語(220)

alias casex dist enum illegal_bins longreal primitive repeat supply0 unique
always casez do event import macromodule priority return supply1 unsigned
always_comb cell edge expect incdir matches process rnmos table use
always_ff chandle else export include medium program rpmos tagged
always_latch changed end extends initial modport property rtran task var
and char endcase extern inout module protected rtranif0 this vectored
assert class endclass final input nand pull0 rtranif1 throughout virtual
assert_strobe clocking endclocking first_match inside negedge pull1 scalared time void
assume cmos endconfig for instance new pulldown sequence timeprecision wait
assign config endfunction force int nmos pullup shortint timeunit wait_order
automatic const endgenerate foreach integer nor pulsestyle_ondetect shortreal tran wand
before constraint endgroup forever interface noshowcancelled pulsestyle_onevent showcancelled tranif0 weak0
begin context endinterface fork intersect not pure signed tranif1 weak1
bind continue endmodule forkjoin join notif0 rand small transition while
bins cover endpackage function join_any notif1 randc solve tri wildcard
binsof covergroup endprimitive generate join_none null randcase specify tri0 wire
bit coverpoint endprogram genvar large or randsequence specparam tri1 with
break cross endproperty highz0 liblist output rcmos static triand within
buf deassign endsequence highz1 library package real string trior wor
bufif0 default endspecify if local packed realtime strong0 trireg xnor
bufif1 defparam endtable iff localparam parameter ref strong1 type xor
byte design endtask ifnone logic pmos reg struct typedef
case disable endtransition ignore_bins longint posedge release super union

IEEE Std. 1800-2005 予約語(221)

SystemVerilog 3.1aにuwire が追加