言語/verilog/Tips/平方根1 - MoriLab.

平方根1

概要

(詳細記述予定)

動作確認

ツール	バージョン	結果
ncverilog		未確認
VCS-MX		未確認
ModelSim		未確認

テストコード

(記述予定)

initial begin
  wait(CHECK_START);
 
  DAT <= #DLY 9;
  REQ <= #DLY 1;  repeat( 1)@(posedge CLK);
  REQ <= #DLY 0;  repeat(20)@(posedge CLK);
 
  DAT <= #DLY 16;
  REQ <= #DLY 1;  repeat( 1)@(posedge CLK);
  REQ <= #DLY 0;  repeat(20)@(posedge CLK);
 
  DAT <= #DLY 100;
  REQ <= #DLY 1;  repeat( 1)@(posedge CLK);
  REQ <= #DLY 0;  repeat(12)@(posedge CLK);
 
  DAT <= #DLY 9;
  REQ <= #DLY 1;  repeat( 1)@(posedge CLK);
  REQ <= #DLY 0;  repeat(11)@(posedge CLK);
 
  DAT <= #DLY 200;
  REQ <= #DLY 1;  repeat( 1)@(posedge CLK);
  REQ <= #DLY 0;  repeat(10)@(posedge CLK);
 
  DAT <= #DLY 22'h3FFFFF;
  REQ <= #DLY 1;  repeat( 1)@(posedge CLK);
  REQ <= #DLY 0;  repeat(20)@(posedge CLK);
 
  DAT <= #DLY 22'h3FFFFF;
  REQ <= #DLY 1;  repeat(20)@(posedge CLK);
  REQ <= #DLY 0;  repeat(20)@(posedge CLK);
 
  $display("");
  $display("NOTE    : [%m] Main Task is completed. -- %t", $time);
  TASKS[0] = 1'b1;
end

ソースコード

(記述予定)

sqrt_mod2

module sqrt_mod2 (
    CLK,
    RST_N,
    REQ,
    DAT,
    ACK,
    NAK,
    SQRT
);
 
  input           CLK;      // C : 
  input           RST_N;    // R : 
  input           REQ;      // I : 
  input   [21:0]  DAT;      // I : 
  output          ACK;      // O : 
  output          NAK;      // O : 
  output  [10:0]  SQRT;     // O : 
 
// **** Wire,Reg **** //
  reg             NAK;
  wire            ACK;
 
  reg     [12:0]  r_req_dly;
  reg     [ 1:0]  r_buf_dat;
  wire    [10:0]  rout;
  wire    [10:0]  delta_out;
  wire            w_busy;
  integer         cnt;
 
// **** assign **** //
 
  assign  ACK      = r_req_dly[12];
  assign  SQRT     = rout;
  assign  w_busy   = | r_req_dly[11:0];
 
  always @(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
      r_req_dly <= 0;
      cnt       <= 0;
    end else begin
      r_req_dly <= {r_req_dly[11:0],REQ & ~w_busy};
 
      if(REQ & w_busy)begin
        NAK <= REQ;
      end else begin
        NAK <= 0;
      end
 
      if(w_busy)begin
        if(cnt==10)begin
          cnt <= 10;
        end else begin
          cnt <= cnt + 1;
        end
        case(cnt)
        0       : r_buf_dat <= DAT[21:20];
        1       : r_buf_dat <= DAT[19:18];
        2       : r_buf_dat <= DAT[17:16];
        3       : r_buf_dat <= DAT[15:14];
        4       : r_buf_dat <= DAT[13:12];
        5       : r_buf_dat <= DAT[11:10];
        6       : r_buf_dat <= DAT[ 9: 8];
        7       : r_buf_dat <= DAT[ 7: 6];
        8       : r_buf_dat <= DAT[ 5: 4];
        9       : r_buf_dat <= DAT[ 3: 2];
        10      : r_buf_dat <= DAT[ 1: 0];
        default : r_buf_dat <= 'bx;
        endcase
      end else begin
        cnt    <= 0;
        r_buf_dat <= 0;
      end
    end
  end
 
  sqrt_calc sqrt_calc (
    .CLK    (CLK      ),
    .RST_N  (RST_N    ),
    .DIN_EN (w_busy   ),
    .DIN    (r_buf_dat),
    .RIN    (rout     ),
    .DELIN  (delta_out),
    .ROUT   (rout     ),
    .DELOUT (delta_out)
  );
endmodule

sqrt_calc

module sqrt_calc (
  CLK,
  RST_N,
  DIN_EN,
  DIN,
  RIN,
  DELIN,
  ROUT,
  DELOUT
);
 
  input           CLK;        // C : Main Clock
  input           RST_N;      // R : Asynchronous Reset
  input           DIN_EN;     // I : Data Enable
  input   [1:0]   DIN;        // I : Data Input
  input   [10:0]  RIN;        // I : Result Input
  input   [10:0]  DELIN;      // I : Delta Input
  output  [10:0]  ROUT;       // O : Result Output
  output  [10:0]  DELOUT;     // O : Delta Output
 
// **** Wire,Reg **** //
  reg     [10:0]  ROUT;       //  Result Output
  reg     [12:0]  r_delout;   //  Delta Output
  wire            w_big_flg;  //  Data Judge Flag
 
  assign  w_big_flg = ({DELIN, DIN} >= {RIN, 2'b01});
  assign  DELOUT    = r_delout[10:0];
 
  always @ (posedge CLK or negedge RST_N) begin
    if (!RST_N) begin
      ROUT      <= 11'h000;
      r_delout  <= 13'h000;
    end
    else if (!DIN_EN) begin
      ROUT      <= 11'h000;
      r_delout  <= 13'h000;
    end
    else begin
      if (w_big_flg) begin
        ROUT     <= {RIN[9:0], 1'b1};
        r_delout <= ({DELIN, DIN} - {RIN, 2'b01});
      end
      else begin
        ROUT     <= {RIN[9:0], 1'b0};
        r_delout <= {DELIN, DIN};
      end
    end
  end
endmodule

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