set_pci_aperture - eslina @ ウィキ

Aubrey Isle 用コード

名称

set_pci_aperture -XXX

書式

void
set_pci_aperture(
    mic_ctx_t * mic_ctx,
    uint32_t    gtt_index,
    uint64_t    phys_addr,
    uint32_t    num_bytes);

引数

mic_ctx

XXX

gtt_index

XXX

phys_addr

XXX

num_bytes

XXX

説明

戻り値

参照

• XXX

実装

host/driver/uos_download.c

309 /*
310   DESCRIPTION::program the PCI aperture as a contiguous window. (only supports upto 4GB memory)
311   PARAMETERS::
312         [in]mic_ctx_t *mic_ctx - mic ctx
313         [in]int gtt_index - beginning gtt entry index
314         [in]uint64_t phy_addr - physical address for PCI aperture
315         [in]uint32_t num_bytes - size of PCI aperture
316   RETURN_VALUE:: None
317   */
318 void
319 set_pci_aperture(mic_ctx_t *mic_ctx, uint32_t gtt_index, uint64_t phy_addr, uint32_t num_bytes)
320 {
321         uint32_t num_pages;
322         uint32_t gtt_entry;
323         int i;
324
325         num_pages = ALIGN(num_bytes, PAGE_SIZE) >> PAGE_SHIFT;
326
327         for (i = 0; i < num_pages; i++) {
328
329                 gtt_entry = ((uint32_t)(phy_addr >> PAGE_SHIFT) + i) << 1 | 0x1u;
330                 GTT_WRITE(gtt_entry, mic_ctx->mmio.va, (gtt_index + i)*sizeof(gtt_entry));
331         }
332
333         // XPU_RACE_CONDITION:
334         // Writing GttTlbFlushReg DOES NOT flush all write transactions from SBOX to GDDR
335         //      because GttTlbFlushReg is an SBOX register and transaction terminates in SBOX
336         // MMIO write must use MIC ringbus to be serializing.
337         // Writing GTT itself DOES serialize: GTT is in MMIO space, and write goes to the ringbus
338         // MemoryBarrier makes sure all writes make it to GDDR before tlbFlush write
339         smp_mb(); // FIXME: only needs SFENCE
340
341         // write any value to cause a flush
342         SBOX_WRITE(1, mic_ctx->mmio.va, SBOX_TLB_FLUSH);
343 }