837-7187

== 837-7187 ==

837-7187はセガのSYSTEM24用ROMボード。

837-7187-01外観

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=== 基板のバージョン ===

シルク形番	パターン形番	etc.
837-7187
837-7187-01	171-5875-01B	ROMボード(小) 2M～8MビットROMを最大8個搭載可能

== 主要チップ,ROM ==

ゲーム名不明ROMボード
BOARD:834-7492-11E

PART No.	MAKER	etc.
MPR-16800	FUJITSU	MB834000-15 MASK ROM or ONE TIME PROM
MPR-16801	FUJITSU	MB834000-15 MASK ROM or ONE TIME PROM
MPR-16802	FUJITSU	MB834000-15 MASK ROM or ONE TIME PROM
MPR-16803	FUJITSU	MB834000-15 MASK ROM or ONE TIME PROM
MPR-16804	FUJITSU	MB834000-15 MASK ROM or ONE TIME PROM
MPR-16805	FUJITSU	MB834000-15 MASK ROM or ONE TIME PROM
MPR-16806	FUJITSU	MB834000-15 MASK ROM or ONE TIME PROM
MPR-16807	FUJITSU	MB834000-15 MASK ROM or ONE TIME PROM
	?	IC2 PAL? EPM5032?

== ROMボード詳細情報 ==

----------------------------------------------------------------------------
Sega System 24 ROM board notes
(C) 2010 Charles MacDonald
----------------------------------------------------------------------------

Overview

The ROM board has a counter that can be read for timing operations, an
interrupt triggering control, and banked ROM.

----------------------------------------------------------------------------
Memory mapping
----------------------------------------------------------------------------

Two jumpers allow the ROM board hardware to be mapped to different
offsets:

- Shorting pins 1,2 of J10,J11 selects B00000-BFFFFF
- Shorting pins 2,3 of J10,J11 selects C00000-CFFFFF

An offset of C00000 will be assumed for this document. The jumpers allow
the ROM board to coexist with the earlier disk drive board and analog I/O
board if needed.

Memory map

C00000-C7FFFF : Unused
C80000-CBFFFF : ROM bank
CC0000-CFFFFF : Registers

----------------------------------------------------------------------------
Registers
----------------------------------------------------------------------------

The EPM5032 chip implements four 8-bit registers. They mapped to D0-D7 and
can be written to by making byte writes to odd addresses or word writes to
even addresses.

The registers are mirrored repeatedly through the range allocated to them.

CC0001 = ROM bank; bits 3-0 (BK3-BK0) can be read and written.
CC0003 = Counter/IRQ mode; bit 0 (MODE) can be read and written.
CC0005 = Counter, bits 7-0 return the current count when read.
CC0007 = Security feature, all 8 bits can be read/written.

Register state after reset

BK3-BK0 are set to zero.
MODE is set to zero.

The counter may be reset to zero, but as it is free running it's hard to
tell.

----------------------------------------------------------------------------
Interrupts
----------------------------------------------------------------------------

When MODE=1, the /INT3 pin is forced low. If bit 0 of $A00005 or $A00007
is set, then a level 1 interrupt is triggered on the main or sub CPU.

When MODE=0, the /INT3 pin is forced high.

There is no functionality to acknowledge the interrupt other than resetting
the MODE bit to 0 within the level 1 interrupt handler.

----------------------------------------------------------------------------
Counter
----------------------------------------------------------------------------

A 10 MHz clock is divided by a 74HC4040 12-bit counter to provide
a 625 KHz (/16) and 9 KHz (/1024) clock. These are fed to the EPM5032
to control an 8-bit binary up-counter.

When MODE=0, the counter wraps from $FF to $00 (modulo 256)
When MODE=1, the counter wraps from $66 to $00 (modulo 103)

Writing to the MODE bit forces the counter to be reset.

The counter is clocked at 625 KHz and the 9 KHz input is used to
accomplish the modulo-103 counting; it does not appear to be a selectable
input to clock the counter by.

----------------------------------------------------------------------------
Jumpers
----------------------------------------------------------------------------

Jumpers 1-9 connect five possible inputs (+5V,GND,BK1,BK2 and BK3) to
five possible outputs (ROM select A and B, ROM pins 1, 30 and 31).

The ROM board has the following jumper settings silk screened on it,
to the right the connections that are made are listed:

Jumper settings        ROM  ROM   P1   P31  P30
(short indicated)      SELB SELA  A19  A18  A17
----------------       ---- ---- ---- ---- ----
2M : J1,J3,J6,J8        BK2  BK1  +5V  +5V  BK0
4M : J2,J3,J7,J9        BK3  BK2  +5V  BK1  BK0
8M : J2,J4,J5,J9        BK3  GND  BK2  BK1  BK0

To see how other jumper settings would work, please see the following
schematic diagram:

http://cgfm2.emuviews.com/img/s24-romboard.png

----------------------------------------------------------------------------
ROM banking
----------------------------------------------------------------------------

The ROM board supports pairs of 8-bit ROMs that are 2, 4, and 8 megabits
in size. ROM data is mapped to a 256K banked area.

Some games may only populate the even or odd ROM sockets such that the
unused byte-lane returns the open bus value when read.

ROMs 1,3,5,7 contain odd data mapped to D0-D7.
ROMs 2,4,6,8 contain even data mapped to D8-D15.

"2M" mode

Devices used:
   Four pairs of 27C020 (2MB max)

Bank values:
   0 = ROM pair 1,2, offset 000000-03FFFF
   1 = ROM pair 1,2, offset 040000-07FFFF

   2 = ROM pair 3,4, offset 000000-03FFFF
   3 = ROM pair 3,4, offset 040000-07FFFF

   4 = ROM pair 5,6, offset 000000-03FFFF
   5 = ROM pair 5,6, offset 040000-07FFFF

   6 = ROM pair 7,8, offset 000000-03FFFF
   7 = ROM pair 7,8, offset 040000-07FFFF

* BK3 is unused, but can still be written and read without affecting
  ROM banking.

"4M" mode

Devices used:
   Four pairs of 27C040 (4MB max)

Bank values:
   0 = ROM pair 1,2, offset 000000-03FFFF
   1 = ROM pair 1,2, offset 040000-07FFFF
   2 = ROM pair 1,2, offset 080000-0BFFFF
   3 = ROM pair 1,2, offset 0C0000-0FFFFF

   4 = ROM pair 3,4, offset 000000-03FFFF
   5 = ROM pair 3,4, offset 040000-07FFFF
   6 = ROM pair 3,4, offset 080000-0BFFFF
   7 = ROM pair 3,4, offset 0C0000-0FFFFF

   8 = ROM pair 5,6, offset 000000-03FFFF
   9 = ROM pair 5,6, offset 040000-07FFFF
   A = ROM pair 5,6, offset 080000-0BFFFF
   B = ROM pair 5,6, offset 0C0000-0FFFFF

   C = ROM pair 7,8, offset 000000-03FFFF
   D = ROM pair 7,8, offset 040000-07FFFF
   E = ROM pair 7,8, offset 080000-0BFFFF
   F = ROM pair 7,8, offset 0C0000-0FFFFF

"8M" mode

Devices used:
   Two pairs of 27C080 (4MB max)

Bank values:
   0 = ROM pair 1,2, offset 000000-03FFFF
   1 = ROM pair 1,2, offset 040000-07FFFF
   2 = ROM pair 1,2, offset 080000-0BFFFF
   3 = ROM pair 1,2, offset 0C0000-0FFFFF
   4 = ROM pair 1,2, offset 100000-13FFFF
   5 = ROM pair 1,2, offset 140000-17FFFF
   6 = ROM pair 1,2, offset 180000-1BFFFF
   7 = ROM pair 1,2, offset 1C0000-1FFFFF

   8 = ROM pair 5,6, offset 000000-03FFFF
   9 = ROM pair 5,6, offset 040000-07FFFF
   A = ROM pair 5,6, offset 080000-0BFFFF
   B = ROM pair 5,6, offset 0C0000-0FFFFF
   C = ROM pair 5,6, offset 100000-13FFFF
   D = ROM pair 5,6, offset 140000-17FFFF
   E = ROM pair 5,6, offset 180000-1BFFFF
   F = ROM pair 5,6, offset 1C0000-1FFFFF

* ROMs in positions 3,4 and 7,8 cannot be accessed.

----------------------------------------------------------------------------
EPM5032
----------------------------------------------------------------------------

Pin assignment
                       +---------+
                   RD# |01 i i 28| 625 KHz clock (10M/16)
          10 MHz clock |02 c i 27| 9 KHz clock (10M/1024)
                  LWR# |03 i o 26| BK0 (To pin 30 of all ROM sockets)
                RESET# |04 i o 25| BK1 (To jumpers)
                 INT3# |05 o o 24| BK2 (To jumpers)
                 DTK1# |06 o o 23| BK3 (To jumpers)
                   +5V |07 s s 22| +5V
                   GND |08 s s 21| GND
                    D0 |09 b b 20| D7
                    D1 |10 b b 19| D6
                    D2 |11 b b 18| D5
                    D3 |12 b b 17| D4
     C80000-CBFFFF CS# |13 i i 16| A1
     CC0000-CFFFFF CS# |14 i i 11| A2
                       +---------+

Pin legend

i = input
o = output
b = bidirectional
c = clock input
s = supply

Pins 13,14,5 change based on J10,J11.

----------------------------------------------------------------------------
Other notes
----------------------------------------------------------------------------

   IC1 : 74HC4040
   IC2 : Altera EPM5032DC (marked "317-0191" on this board)
   IC3 : 74LS138
IC4-44 : 32-pin sockets that support 27C020 through 27C080

CN2 is an unpopulated high-density connector that brings most of the
memory signals to the edge of the board.

There are no wait states inserted when accessing the registers and
banked ROM, and no register settings seem to cause wait states to be added.

----------------------------------------------------------------------------
End
----------------------------------------------------------------------------