| uPD65003 | uPD65002 | uPD65010 | uPD65020 | |
| Number of cells | 427 | 858 | 1368 | 2112 |
| Configuration | 61 rows x 7 Columns | 66 rows x 13 Columns | 76 rows x 18 Columns | 96 rows x 22 Columns |
| Number of Input buffers | 36 | 48 | 64 | 78 |
| Number of Output buffers | 36 | 48 | 64 | 78 |
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| ・VDD:4.5~5.5V ・High speed:3.0ns/gate(with fan-out of 3 and 3-mm wiring) ・Low power:30uW/gate/MHz ・Quick turnaround time:8-12 weeks ・Simple interface to customer's circuit diagram and test pattern sheets ・Fully supported by advanced CAD -Logic simulation -Automatic placement and routing -Test progtam generation -Delay simulation ・Direct access to CAD simulation -Designers can use their own terminals through a local network to an NEC design center for logic simulation ・Four type of output buffers -Nomal -Open drain -Three-state -Bidirectional ・Wide choice of DIP,QIP,PGA,and flat package to suit unique applications |
