作業テーブル/PIC12F1822/3.0 MEMORY ORGANIZATION - alphaomega @ ウィキ

※上記の広告は60日以上更新のないWIKIに表示されています。更新することで広告が下部へ移動します。

---

3.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory
• Data Memory
  • Core Registers
  • Special Function Registers
  • General Purpose RAM
  • Common RAM
  • Device Memory Maps
  • Special Function Registers Summary
• Data EEPROM memory (*1)

Note 1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section 11.0 “Data EEPROM and Flash Program Memory Control”.

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH
• Stack
• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space.
Table 3-1 shows the memory sizes implemented for the PIC12(L)F1822/16(L)F1823 family.
Accessing a location above these boundaries will cause a wrap-around within the implemented memory space.

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device	Program Memory Space (Words)	Last Program Memory Address
PIC12(L)F1822 PIC16(L)F1823	2,048	07FFh

FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC12(L)F1822/16(L)F1823

A B C

Top > 作業テーブル > PIC12F1822 > 3.0 MEMORY ORGANIZATION

---

*1 Note 1